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vishay siliconix si9105 document number: 70003 s-70497-rev. i, 19-mar-07 www.vishay.com 1 1-w high-voltage switchmode regulator features ? ccitt compatible ? current-mode control ? low power consumption (less than 5 mw) ? 10 to 120 v input range ? 200 v, 250 ma mosfet ? internal start-up circuit ? current-mode control ? shutdown and reset description the si9105 high-voltage switchmode regulator is a mono- lithic bic/dmos integrated circuit which contains most of the components necessary to implem ent a high-efficiency dc/dc converter in isdn terminals up to 3 watts. a 0.5 ma max supply current makes possible the design of a dc/dc con- verter with 60 % efficiency at 25 mw, therefore meeting the recommended performance under the ccitt i.430 specifi- cations. this device may be used with an appropriate transformer to implement isolated flyback power converter topologies to provide single or multiple regul ated dc outputs (i.e., 5 v). the si9105 is available in both standard and lead (pb)-free 16-pin wide-body soic, 14-pin plastic dip and 20-pin plcc packages which are specified to operate over the industrial temperature range of - 40 c to 85 c. functional block diagram + - - + + - + - + - fb comp discharge osc 2 v ref gen r s q r s q drain source current-mode comparator c/l 1.2 v undervoltage comparator reset 8.7 v 9.3 v bias current sources to internal circuits comparator error amplifier v ref v cc +v in v cc shutdown 4 v (1 %) clock (? f osc ) osc out osc in -v in (body)
www.vishay.com 2 document number: 70003 s-70497-rev. i, 19-mar-07 vishay siliconix si9105 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 6 mw/c above 25 c. c. derate 7.2 mw/c above 25 c. d. derate 11.2 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit voltages referenced to - v in (v cc < + v in + 0.3 v) v cc 15 v +v in 120 v ds 200 i d (peak) (300 s pulse, 2 % duty cycle) 2 a i d (rms) 250 ma logic inputs (reset, shutdown , osc in) - 0.3 v to v cc + 0.3 v v linear inputs (feedback, source) - 0.3 v to 7 v hv pre-regulator input current (continuous) 5 ma storage temperature - 65 to 125 c operating temperature - 40 to 85 junction temperature (t j ) 150 power dissipation (package) a 14-pin plastic dip (j suffix) b 750 mw 16-pin plastic wide-b ody soic (w suffix) c 900 20-pin plcc (n suffix) d 1400 thermal impedance ( ja ) 14-pin plastic dip 167 c/w 16-pin plastic wide-body soic 140 20-pin plcc 90 recommended operating range parameter limit unit voltages referenced to - v in v cc 10 to 13.5 v + v in 10 to 120 f osc 40 khz to 1 mhz r osc 25 k to 1 m linear inputs 0 to v cc - 3 v v digital inputs 0 to v cc specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 820 k , r osc = 910 k limits unit temp b min c typ d max c reference output voltage v r osc in = - v in (osc disabled) r l = 10 m room 3.92 4.00 4.08 v output impedance e z out osc in = - v in room 15 300 45 k short circuit current i sref osc in = - v in , v ref = - v in room 70 100 130 a temperature stability e t ref osc in = - v in full 0.25 1.0 mv/c long term stability e t = 1000 h, t a = 125 c room 5.00 25.00 mv oscillator maximum frequency e f max r osc = 0 room 1 3 mhz initial accuracy f osc see note e room 32 40 48 khz voltage stability f/f f/f = f(13.5 v) - f(9.5 v)/f(9.5 v) room 10 15 % temperature coefficient e t osc full 200 500 ppm/c
document number: 70003 s-70497-rev. i, 19-mar-07 www.vishay.com 3 vishay siliconix si9105 notes: a. refer to process option flowchart for additional information. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, no t subject to production test. f. c stray pin 8 = 5 pf. g .temperature coefficient of r ds(on) is 0.75 % per c, typical. specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 820 k , r osc = 910 k limits unit temp b min c typ d max c error amplifier feedback input voltage v fb fb tied to comp osc in = - v in (osc disabled) room 3.96 4 4.04 v input bias current i fb osc in = - v in , v fb = 4 v room 25 500 na open loop voltage gain e a vol osc in = - v in (osc disabled) room 60 80 db input offset voltage v os osc in = - v in room 15 40 mv unity gain bandwidth e bw room 0.5 0.8 mhz dynamic output impedance z out room 1 k output current i out source (v fb = 3.4 v) room - 1.2 - 0.32 ma sink (v fb = 4.5 v) room 0.05 0.08 power supply rejection psrr 10 v v cc 13.5 v room 70 db current limit threshold voltage v source r l = 100 from drain to v cc v fb = 0 v room 0.8 1.0 1.2 v delay to output e t d r l = 100 from drain to v cc v source = 1.5 v, see figure 1 room 200 300 ns input voltage + v in i in = 10 a room 120 v input leakage current + i in v cc 10 v room 10 a pre-regulator start-up current i start pulse width 300 s, v cc = 7 v room 8 15 ma v cc pre-regulator turn-off threshold voltage v reg i pre-regulator = 10 a room 7.5 9.3 9.7 v undervoltage lockout v uvlo r l = 100 from drain to v cc see detailed description room 7.0 8.7 9.2 v reg - v uvlo v delta room 0.25 0.5 supply supply current i cc room 0.35 0.5 ma bias current i bias room 7.5 a shutdown delay t sd v source = - v in , see figure 2 room 50 100 ns shutdown pulse width t sw see figure 3 room 50 reset pulse width t rw room 50 latching pulse width shutdown and reset low t lw room 25 input low voltage v il room 2.0 v input high voltage v ih room 8.0 input current input voltage high i ih v in = 10 v room 1 5 a input current input voltage low i il v in = 0 v room - 35 - 25 mosfet switch breakdown voltage v (br)dss i drain = 100 a full 200 220 v drain-source on resistance g r ds(on) i drain = 100 ma room 5 7 drain off leakage current i dss v drain = 100 v room 10 a drain capacitance c ds room 35 pf
www.vishay.com 4 document number: 70003 s-70497-rev. i, 19-mar-07 vishay siliconix si9105 timing waveforms typical characteristics figure 1. drain source 0 0 v cc - 10 % 1.5 v - 50 % t d t r 10 ns figure 2. drain 0 0 - v cc v cc - shutdown 10 % 50 % t f 10 ns t sd figure 3. 0 - reset 0 - v cc v cc shutdown 50 % 50 % 50 % 50 % t sw t lw t rw t r , t f 10 ns 50 % figure 4. output switching frequency vs. oscillator resistance (hz) 1 m 10 k 100 k 10 k 100 k 1 m f out r osc - oscillator resistance ( )
document number: 70003 s-70497-rev. i, 19-mar-07 www.vishay.com 5 vishay siliconix si9105 pin configurations 1 2 3 4 5 6 7 14 13 12 11 10 9 8 pdip-14 top view 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 plcc-20 to p view 13 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 so-16 (wide-body) top view pin description function pin number 14-pin plastic dip 16-pin soic 20-pin plcc source 4 1 7 - v in 528 v cc 649 osc out 7510 osc in 8611 discharge 9 7 12 v ref 10 8 14 shutdown 11 9 16 reset 12 10 17 comp 13 11 18 fb 14 12 20 bias 1 13 2 + v in 2143 drain 3 16 5 nc 3, 15 1, 4, 6, 13, 15, 19 ordering information standard part number lead (pb)-free part number temperature range package si9105dj02 si9105dj02-e3 - 40 to 85 c pdip-14 si9105dw soic-16 (wb) si9105dw-t1 (with tape and reel) SI9105DW-T1-E3 (with tape and reel) si9105dn02 si9105dn02-e3 plcc-20 si9105dn02-t1 (with tape and reel) si9105dn02-t1-e3 (with tape and reel)
www.vishay.com 6 document number: 70003 s-70497-rev. i, 19-mar-07 vishay siliconix si9105 detailed description pre-regulator/start-up section due to the low quiescent current requirement of the si9105 control circuitry, bias power can be supplied from the unreg- ulated input power source, from an external regulated low- voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. when power is first applied during start-up, + v in will draw a constant current. the magnitude of this current is determined by a high-voltage depletion mosfet device which is con- nected between + v in and v cc . this start-up circuitry pro- vides initial power to the ic by charging an external bypass capacitance connected to the v cc pin. the constant current is disabled when v cc exceeds 9.3 v. if v cc is not forced to exceed the 9.3 v threshold, then v cc will be regulated to a nominal value of 9.3 v by the pre-regulator circuit. as the supply voltage rises toward the normal operating con- ditions, an internal undervoltage (uv) lockout circuit keeps the output mosfet disabled until v cc exceeds the under- voltage lockout threshold (typically 8.7 v). this guarantees that the control logic will be functioning properly and that suf- ficient gate drive voltage is available before the mosfet turns on. the design of the ic is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. power dissipation can be minimized by providing an external power source to v cc such that the constant current source is always disabled. bias to properly set the bias for the si9105, a 820 k resistor should be tied from bias to - v in . this determines the mag- nitude of bias current in all of the analog sections and the pull-up current for the shutdown and reset pins. the current flowing in the bias resistor is nominally 7.5 a. reference section the reference section of the si9105 consists of a tempera- ture compensated buried zener and trimmable divider net- work. the output of the reference section is connected internally to the non-inverting input of the error amplifier. nominal refer- ence output voltage is 4 v. the trimming procedure that is used on the si9105 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1 % of 4 v. this automatically compensates for the input offset voltage in the error amplifier. the output impedance of the reference section has been purposely made high so that a low impedance external volt- age source can be used to override the internal voltage source, if desired, without otherwise altering the perfor- mance of the device. error amplifier closed-loop regulation is prov ided by the error amplifier, whose 1 k dynamic output impedance enables it to be used with feedback compensation (unlike transconductance amplifiers). a mos differential input stage provides for low input current. the noninverting input to the error amplifier (v ref ) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. oscillator section the oscillator consists of a ring of cmos inverters, capaci- tors, and a capacitor discharge switch. frequency is set by an external resistor between the osc in and osc out pins. (see typical characteristics gr aph of resistor value vs. fre- quency.) the discharge pin should be tied to - v in for nor- mal internal oscillator operation. a frequency divider in the logic section limits switch du ty cycle to a maximum of 50 % by locking the switching frequency to one half of the oscillator frequency. remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the osc in terminal. for a 5 v pulse amplitude and 0.5 s pulse width, typical val- ues would be 100 pf in series with 3 k to osc in.
document number: 70003 s-70497-rev. i, 19-mar-07 www.vishay.com 7 vishay siliconix si9105 detailed description (cont?d) shutdown and reset shutdown and reset are intend ed for overriding the output mosfet switch via exte rnal control logic. the two inputs are fed through a latch preceding the output switch. depending on the logic state of reset, shutdown can be either a latched or unlatched input. the output is off when- ever shutdown is low. by simultaneously having shut- down and reset low, the latch is set and shutdown has no effect until reset goes high. the truth table for these inputs is given in table 1. both pins have internal current source pull-ups and can be left disconnected when not in us e. an added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the shutdown pin to provide vari- able shutdown time. output switch the output switch is a 7 , 200 v lateral dmos transistor. like discrete mosfets, the sw itch contains an intrinsic body-drain diode. however, t he body contact in the si9105 is connected internally to - v in and is independent of the source. table 1. truth table for the shutdown and reset pins applications vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?70003 . shutdown reset output h h normal operation h normal operation (no change) l h off (not latched) l l off (latched) l off (latched, no change) figure 5. ccitt compatible isdn terminal power supply 20 f si9105dj 1n5819 1n5819 8 7 10 9 2 3 4 output + 5 v 5 v 150 k 5.6 v 12 v 1n4148 71.5 k 1 % 15 k 47.5 k 1 % 820 k 910 k nc nc + - input gnd ( gnd plane ) 3 6 14 13 4 8 7 12 10 1 59 211 0.1 f 0.1 f 0.22 f 1 f 0.1 f 0.1 f 220 f 47 f l p = 3.8 mh 0.1 f +v in 3.9 -
ecn: s-40079?rev. a, 02-feb-04 dwg: 5910 0.2025 0.001 0.06 0.002d cavity no. 0.295 0.001 0.070 0.005 0.1475 0.001 0.055 0.005 pin 1 indicator 0.047 0.007 0.001 dp surface polished 0.010 0.334 0.005 r0.004 r0.008 r0.009 r0.004 0.032 0.005 4 2 0.041 0.001 0.405 0.001 0.091 0.001 0.017 0.0003 0.050 typ. 0.006 0.002 0.098 0.002 0.334 0.005 0.291 0.001 0.295 0.001 0.406 0.004 r0.004 7 (4 ) 0.020 45 detail a detail a 1 2345678 16 15 14 13 12 11 10 9 all dimensions in inches package information vishay siliconix document number: 72805 28-jan-04 www.vishay.com 1 soic (wide-body): 16-lead (power ic only)
0.101 mm 0.004 d ? square d 1 ? square a 2 b 1 e 1 a 1 d 2 b a package information vishay siliconix document number: 72812 28-jan-04 www.vishay.com 1 plcc: 2o-lead (power ic only) millimeters inches dim min max min max a 4.20 4.57 0.165 0.180 a 1 2.29 3.04 0.090 0.120 a 2 0.51 ? 0.020 ? b 0.331 0.553 0.013 0.021 b 1 0.661 0.812 0.026 0.032 d 9.78 10.03 0.385 0.395 d 1 8.890 9.042 0.350 0.356 d 2 7.37 8.38 0.290 0.330 e 1 1.27 bsc 0.050 bsc ecn: s-40081?rev. a, 02-feb-04 dwg: 5917
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 1234567 14 13 12 11 10 9 8 package information vishay siliconix document number: 72814 28-jan-04 www.vishay.com 1 pdip: 14-lead (power ic only) millimeters inches dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 17.27 19.30 0.680 0.760 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 1.02 2.03 0.040 0.080 ecn: s-40081?rev. a, 02-feb-04 dwg: 5919
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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